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adc08d500 high performance, low power, dual 8-bit, 500 msps a/d converter general description the adc08d500 is a dual, low power, high performance cmos analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 800 msps. consum- ing a typical 1.4 watts at 500 msps from a single 1.9 volt supply, this device is guaranteed to have no missing codes over the full operating temperature range. the unique folding and interpolating architecture, the fully differential compara- tor design, the innovative design of the internal sample-and- hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond nyquist, producing a high 7.5 enob with a 250 mhz input signal and a 500 mhz sample rate while providing a 10 -18 b.e.r. output formatting is offset binary and the lvds digital outputs are compliant with ieee 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8v and 1.2v. each converter has a 1:2 demultiplexer that feeds two lvds buses and reduces the output data rate on each bus to half the sampling rate. the two converters can be interleaved and used as a single 1 gsps adc. the converter typically consumes less than 3.5 mw in the power down mode and is available in a 128-lead, thermally enhanced exposed pad lqfp and operates over the indus- trial (-40?c t a +85?c) temperature range. features n internal sample-and-hold n single +1.9v 0.1v operation n choice of sdr or ddr output clocking n interleave mode for 2x sampling rate n multiple adc synchronization capability n guaranteed no missing codes n serial interface for extended control n fine adjustment of input full-scale range and offset n duty cycle corrected sample clock key specifications n resolution 8 bits n max conversion rate 500 msps (min) n bit error rate 10 -18 (typ) n enob @ 250 mhz input 7.5 bits (typ) n dnl 0.15 lsb (typ) n power consumption operating 1.4 w (typ) power down mode 3.5 mw (typ) applications n direct rf down conversion n digital oscilloscopes n satellite set-top boxes n communications systems n test instrumentation block diagram 20121453 may 2005 high performance, low power, dual 8-bit, 500 msps a/d converter 2005 national semiconductor corporation ds201214 www.national.com
ordering information industrial temperature range (-40?c < t a < +85?c) ns package ADC08D500CIYB 128-pin exposed pad lqfp adc08d500eval evaluation board pin configuration 20121401 * exposed pad on back of package must be soldered to ground plane to ensure rated performance. adc08d500 www.national.com 2
pin descriptions and equivalent circuits pin functions pin no. symbol equivalent circuit description 3 outv / sclk output voltage amplitude and serial interface clock. tie this pin high for normal differential dclk and data amplitude. ground this pin for a reduced differential output amplitude and reduced power consumption. see section 1.1.6. when the extended control mode is enabled, this pin functions as the sclk input which clocks in the serial data.see section 1.2 for details on the extended control mode. see section 1.3 for description of the serial interface. 4 outedge / ddr / sdata dclk edge select, double data rate enable and serial data input. this input sets the output edge of dclk+ at which the output data transitions. (see section 1.1.5.2). when this pin is floating or connected to 1/2 the supply voltage, ddr clocking is enabled. when the extended control mode is enabled, this pin functions as the sdata input. see section 1.2 for details on the extended control mode. see section 1.3 for description of the serial interface. 15 dclk_rst dclk reset. a positive pulse on this pin is used to reset and synchronize the dclk outs of multiple converters. see section 1.5 for detailed description. 26 29 pd pdq power down pins. a logic high on the pd pin puts the entire device into the power down mode. a logic high on the pdq pin puts only the "q" adc into the power down mode. 30 cal calibration cycle initiate. a minimum 80 input clock cycles logic low followed by a minimum of 80 input clock cycles high on this pin initiates the self calibration sequence. see section 2.4.2 for an overview of self-calibration and section 2.4.2.2 for a description of on-command calibration. 14 fsr/ece full scale range select and extended control enable. in non-extended control mode, a logic low on this pin sets the full-scale differential input range to 650 mv p-p . a logic high on this pin sets the full-scale differential input range to 870 mv p-p . see section 1.1.4. to enable the extended control mode, whereby the serial interface and control registers are employed, allow this pin to float or connect it to a voltage equal to v a /2. see section 1.2 for information on the extended control mode. 127 caldly / des / scs calibration delay, dual edge sampling and serial interface chip select. with a logic high or low on pin 14, this pin functions as calibration delay and sets the number of clock cycles after power up before calibration begins (see section 1.1.1). with pin 14 floating, this pin acts as the enable pin for the serial interface input and the caldly value becomes 0b (short delay with no provision for a long power-up calibration delay). when this pin is floating or connected to a voltage equal to v a /2, des (dual edge sampling) mode is selected where the "i" input is sampled at twice the clock rate and the "q" input is ignored. see section 1.1.5.1. adc08d500 www.national.com 3
pin descriptions and equivalent circuits (continued) pin functions pin no. symbol equivalent circuit description 18 19 clk+ clk- lvds clock input pins for the adc. the differential clock signal must be a.c. coupled to these pins. the input signal is sampled on the falling edge of clk+. see section 1.1.2 for a description of acquiring the input and section 2.3 for an overview of the clock inputs. 11 10 . 22 23 v in i+ v in i? . v in q+ v in q? analog signal inputs to the adc. the differential full-scale input range is 650 mv p-p when the fsr pin is low, or 870 mv p-p when the fsr pin is high. 7v cmo common mode voltage. the voltage output at this pin is required to be the common mode input voltage at v in + and v in ? when d.c. coupling is used. this pin should be grounded when a.c. coupling is used at the analog inputs. this pin is capable of sourcing or sinking 100?. see section 2.2. 31 v bg bandgap output voltage capable of 100 ? source/sink. 126 calrun calibration running indication. this pin is at a logic high when calibration is running. 32 r ext external bias resistor connection. nominal value is 3.3k-ohms ( 0.1%) to ground. see section 1.1.1. 34 35 tdiode_p tdiode_n temperature diode positive (anode) and negative (cathode) for die temperature measurements. see section 2.6.2. adc08d500 www.national.com 4
pin descriptions and equivalent circuits (continued) pin functions pin no. symbol equivalent circuit description 83/78 84/77 85/76 86/75 89/72 90/71 91/70 92/69 93/68 94/67 95/66 96/65 100/61 101/60 102/59 103/58 di7? / dq7? di7+ / dq7+ di6? / dq6? di6+ / dq6+ di5? / dq5? di5+ / dq5+ di4? / dq4? di4+ / dq4+ di3? / dq3? di3+ / dq3+ di2? / dq2? di2+ / dq2+ di1? / dq1? di1+ / dq1+ di0? / dq0? di0+ / dq0+ i and q channel lvds data outputs that are not delayed in the output demultiplexer. compared with the did and dqd outputs, these outputs represent the later time samples. these outputs should always be terminated with a 100 ? differential resistor. 104/57 105/56 106/55 107/54 111/50 112/49 113/48 114/47 115/46 116/45 117/44 118/43 122/39 123/38 124/37 125/36 did7? / dqd7? did7+ / dqd7+ did6? / dqd6? did6+ / dqd6+ did5? / dqd5? did5+ / dqd5+ did4? / dqd4? did4+ / dqd4+ did3? / dqd3? did3+ / dqd3+ did2? / dqd2? did2+ / dqd2+ did1? / dqd1? did1+ / dqd1+ did0? / dqd0? did0+ / dqd0+ i and q channel lvds data outputs that are delayed by one clk cycle in the output demultiplexer. compared with the di/dq outputs, these outputs represent the earlier time sample. these outputs should always be terminated with a 100 ? differential resistor. 79 80 or+ or- out of range output. a differential high at these pins indicates that the differential input is out of range (outside the range 325 mv or 435 mv as defined by the fsr pin). 82 81 dclk+ dclk- differential clock outputs used to latch the output data. delayed and non-delayed data outputs are supplied synchronous to this signal. this signal is at 1/2 the input clock rate in sdr mode and at 1/4 the input clock rate in the ddr mode. 2, 5, 8, 13, 16, 17, 20, 25, 28, 33, 128 v a analog power supply pins. bypass these pins to ground. adc08d500 www.national.com 5
pin descriptions and equivalent circuits (continued) pin functions pin no. symbol equivalent circuit description 40, 51 ,62, 73, 88, 99, 110, 121 v dr output driver power supply pins. bypass these pins to dr gnd. 1, 6, 9, 12, 21, 24, 27, 41 gnd ground return for v a . 42, 53, 64, 74, 87, 97, 108, 119 dr gnd ground return for v dr . 52, 63, 98, 109, 120 nc no connection. make no connection to these pins. adc08d500 www.national.com 6
absolute maximum ratings (notes 1, 2) if military/aerospace specified devices are required, please contact the national semiconductor sales office/ distributors for availability and specifications. supply voltage (v a ,v dr ) 2.2v voltage on any input pin ?0.15v to (v a +0.15v) ground difference |gnd - dr gnd| 0v to 100 mv input current at any pin (note 3) 25 ma package input current (note 3) 50 ma power dissipation at t a = 85?c 2.0 w esd susceptibility (note 4) human body model machine model 2500v 250v soldering temperature, infrared, 10 seconds (note 5) 235?c storage temperature ?65?c to +150?c operating ratings (notes 1, 2) ambient temperature range ?40?c t a +85?c supply voltage (v a ) +1.8v to +2.0v driver supply voltage (v dr ) +1.8v to v a analog input common mode voltage v cmo 50mv v in +, v in - voltage range (maintaining common mode) 200mv to v a ground difference (|gnd - dr gnd|) 0v clk pins voltage range 0v to v a differential clk amplitude 0.4v p-p to 2.0v p-p package thermal resistance package ja jc (top of package) j-pad (thermal pad) 128-lead exposed pad lqfp 25?c / w 10?c / w 2.8?c / w converter electrical characteristics the following specifications apply after calibration for v a =v dr = +1.9v dc , outv = 1.9v, v in fsr (a.c. coupled) = differential 870mv p-p ,c l = 10 pf, differential, a.c. coupled sinewave input clock, f clk = 500 mhz at 0.5v p-p with 50% duty cycle, v bg = floating, non-extended control mode, sdr mode, r ext = 3300 ? 0.1%, analog signal source impedance = 100 ? differen- tial. boldface limits apply for t a =t min to t max . all other limits t a = 25?c, unless otherwise noted. (notes 6, 7) symbol parameter conditions typical (note 8) limits (note 8) units (limits) static converter characteristics inl integral non-linearity dc coupled, 1mhz sine wave overanged 0.3 0.9 lsb (max) dnl differential non-linearity dc coupled, 1mhz sine wave overanged 0.15 0.6 lsb (max) resolution with no missing codes 8 bits v off offset error -0.45 ?1.5 0.5 lsb (min) lsb (max) v off _adj input offset adjustment range extended control mode 45 mv pfse positive full-scale error (note 9) ?0.6 25 mv (max) nfse negative full-scale error (note 9) ?1.31 25 mv (max) fs_adj full-scale adjustment range extended control mode 20 15 %fs normal mode (non des) dynamic converter characteristics fpbw full power bandwidth normal (non des) mode 1.7 ghz b.e.r. bit error rate 10 -18 error/sample gain flatness d.c. to 500 mhz 0.5 dbfs enob effective number of bits f in = 50 mhz, v in = fsr ? 0.5 db 7.5 bits f in = 100 mhz, v in = fsr ? 0.5 db 7.5 7.1 bits (min) f in = 248 mhz, v in = fsr ? 0.5 db 7.5 7.1 bits (min) sinad signal-to-noise plus distortion ratio f in = 50 mhz, v in = fsr ? 0.5 db 47 db f in = 100 mhz, v in = fsr ? 0.5 db 47 44.5 db (min) f in = 248 mhz, v in = fsr ? 0.5 db 47 44.5 db (min) adc08d500 www.national.com 7
converter electrical characteristics (continued) the following specifications apply after calibration for v a =v dr = +1.9v dc , outv = 1.9v, v in fsr (a.c. coupled) = differential 870mv p-p ,c l = 10 pf, differential, a.c. coupled sinewave input clock, f clk = 500 mhz at 0.5v p-p with 50% duty cycle, v bg = floating, non-extended control mode, sdr mode, r ext = 3300 ? 0.1%, analog signal source impedance = 100 ? differen- tial. boldface limits apply for t a =t min to t max . all other limits t a = 25?c, unless otherwise noted. (notes 6, 7) symbol parameter conditions typical (note 8) limits (note 8) units (limits) normal mode (non des) dynamic converter characteristics snr signal-to-noise ratio f in = 50 mhz, v in = fsr ? 0.5 db 48 db f in = 100 mhz, v in = fsr ? 0.5 db 48 45.3 db (min) f in = 248 mhz, v in = fsr ? 0.5 db 47.5 45.3 db (min) thd total harmonic distortion f in = 50 mhz, v in = fsr ? 0.5 db -55 db f in = 100 mhz, v in = fsr ? 0.5 db -55 ?47.5 db (max) f in = 248 mhz, v in = fsr ? 0.5 db -55 ?47.5 db (max) 2nd harm second harmonic distortion f in = 50 mhz, v in = fsr ? 0.5 db ?60 db f in = 100 mhz, v in = fsr ? 0.5 db ?60 db f in = 248 mhz, v in = fsr ? 0.5 db ?60 db 3rd harm third harmonic distortion f in = 50 mhz, v in = fsr ? 0.5 db ?65 db f in = 100 mhz, v in = fsr ? 0.5 db ?65 db f in = 248 mhz, v in = fsr ? 0.5 db ?65 db sfdr spurious-free dynamic range f in = 50 mhz, v in = fsr ? 0.5 db 55 db f in = 100 mhz, v in = fsr ? 0.5 db 55 47.5 db (min) f in = 248 mhz, v in = fsr ? 0.5 db 55 47.5 db (min) imd intermodulation distortion f in1 = 121 mhz, v in =fsr?7db f in2 = 126 mhz, v in =fsr?7db -50 db out of range output code (in addition to or output high) (v in +)?(v in ?) > + full scale 255 (v in +)?(v in ?) < ? full scale 0 interleave mode (des pin 127=float) - dynamic converter characteristics fpbw (des) full power bandwidth dual edge sampling mode 900 mhz enob effective number of bits f in = 100 mhz, v in = fsr ? 0.5 db 7.4 7.0 bits (min) f in = 248 mhz, v in = fsr ? 0.5 db 7.4 7.0 bits (min) sinad signal to noise plus distortion ratio f in = 100 mhz, v in = fsr ? 0.5 db 46.3 43.9 db (min) f in = 248 mhz, v in = fsr ? 0.5 db 46.3 43.9 db (min) snr signal to noise ratio f in = 100 mhz, v in = fsr ? 0.5 db 46.7 44.1 db (min) f in = 248 mhz, v in = fsr ? 0.5 db 46.7 44.1 db (min) thd total harmonic distortion f in = 100 mhz, v in = fsr ? 0.5 db -58 -49 db (min) f in = 248 mhz, v in = fsr ? 0.5 db -58 -49 db (min) 2nd harm second harmonic distortion f in = 100 mhz, v in = fsr ? 0.5 db -60 db f in = 248 mhz, v in = fsr ? 0.5 db -60 db 3rd harm third harmonic distortion f in = 100 mhz, v in = fsr ? 0.5 db -64 db f in = 248 mhz, v in = fsr ? 0.5 db -64 db sfdr spurious free dynamic range f in = 248 mhz, v in = fsr ? 0.5 db 57 47 db(min) f in = 248 mhz, v in = fsr ? 0.5 db 57 47 db(min) analog input and reference characteristics v in full scale analog differential input range fsr pin 14 low 650 570 mv p-p (min) 730 mv p-p (max) fsr pin 14 high 870 790 mv p-p (min) 950 mv p-p (max) v cmi analog input common mode voltage v cmo v cmo ?50 v cmo +50 mv (min) mv (max) adc08d500 www.national.com 8
converter electrical characteristics (continued) the following specifications apply after calibration for v a =v dr = +1.9v dc , outv = 1.9v, v in fsr (a.c. coupled) = differential 870mv p-p ,c l = 10 pf, differential, a.c. coupled sinewave input clock, f clk = 500 mhz at 0.5v p-p with 50% duty cycle, v bg = floating, non-extended control mode, sdr mode, r ext = 3300 ? 0.1%, analog signal source impedance = 100 ? differen- tial. boldface limits apply for t a =t min to t max . all other limits t a = 25?c, unless otherwise noted. (notes 6, 7) symbol parameter conditions typical (note 8) limits (note 8) units (limits) analog input and reference characteristics c in analog input capacitance, normal operation (notes 10, 11) differential 0.02 pf each input pin to ground 1.6 pf analog input capacitance, des mode (notes 10, 11) differential 0.08 pf each input pin to ground 2.2 pf r in differential input resistance 100 94 ? (min) 106 ? (max) analog output characteristics v cmo common mode output voltage 1.26 0.95 1.45 v (min) v (max) v cmo_lvl v cmo input threshold to set dc coupling mode v a = 1.8v 0.60 v v a = 2.0v 0.66 v tc v cmo common mode output voltage temperature coefficient t a = ?40?c to +85?c 118 ppm/?c c load v cmo maximum v cmo load capacitance 80 pf v bg bandgap reference output voltage i bg = 100 ? 1.26 1.20 1.33 v (min) v (max) tc v bg bandgap reference voltage temperature coefficient t a = ?40?c to +85?c, i bg = 100 ? 28 ppm/?c c load v bg maximum bandgap reference load capacitance 80 pf temperature diode characteristics ? v be temperature diode voltage 192 ? vs. 12 ?, t j = 25?c 71.23 mv 192 ? vs. 12 ?, t j = 85?c 85.54 mv channel-to-channel characteristics offset error match 1 lsb positive full-scale error match zero offset selected in control register 1 lsb negative full-scale error match zero offset selected in control register 1 lsb phase matching (i,q) f in = 1.0 ghz < 1 degree x-talk crosstalk from i (agressor) to q (victim) channel aggressor = 867 mhz f.s. victim = 100 mhz f.s. ?71 db x-talk crosstalk from q (agressor) to i (victim) channel aggressor = 867 mhz f.s. victim = 100 mhz f.s. -71 db clock input characteristics v id differential clock input level sine wave clock 0.6 0.4 2.0 v p-p (min) v p-p (max) square wave clock 0.6 0.4 2.0 v p-p (min) v p-p (max) i i input current v in =0orv in =v a 1a c in input capacitance (notes 10, 11) differential 0.02 pf each input to ground 1.5 pf adc08d500 www.national.com 9
converter electrical characteristics (continued) the following specifications apply after calibration for v a =v dr = +1.9v dc , outv = 1.9v, v in fsr (a.c. coupled) = differential 870mv p-p ,c l = 10 pf, differential, a.c. coupled sinewave input clock, f clk = 500 mhz at 0.5v p-p with 50% duty cycle, v bg = floating, non-extended control mode, sdr mode, r ext = 3300 ? 0.1%, analog signal source impedance = 100 ? differen- tial. boldface limits apply for t a =t min to t max . all other limits t a = 25?c, unless otherwise noted. (notes 6, 7) symbol parameter conditions typical (note 8) limits (note 8) units (limits) digital control pin characteristics v ih logic high input voltage (note 12) 0.85 x v a v (min) v il logic low input voltage (note 12) 0.15 x v a v (max) c in input capacitance (notes 11, 13) each input to ground 1.2 pf digital output characteristics v od lvds differential output voltage measured differentially, outv = v a , v bg = floating, (note 15) 710 400 mv p-p (min) 920 mv p-p (max) measured differentially, outv = gnd, v bg = floating, (note 15) 510 280 mv p-p (min) 720 mv p-p (max) ? v o diff change in lvds output swing between logic levels 1mv v os output offset voltage, see figure 1 v bg = floating 800 mv v os output offset voltage, see figure 1 v bg =v a (note 15) 1200 mv ? v os output offset voltage change between logic levels 1mv i os output short circuit current output+ & output- connected to 0.8v ?4 ma z o differential output impedance 100 ohms v oh cal_run h level output i oh = -400ua (note 12) 1.65 1.5 v v ol cal_run l level output i oh = 400ua (note 12) 0.15 0.3 v power supply characteristics i a analog supply current pd = pdq = low pd = low, pdq = high pd = pdq = high 561 340 1.8 665 408 ma (max) ma ma i dr output driver supply current pd = pdq = low pd = low, pdq = high pd = pdq = high 200 112 0.012 275 157 ma (max) ma (max) ma p d power consumption pd = pdq = low pd = low, pdq = high pd = pdq = high 1.4 0.8 3.5 1.78 1.0 w (max) w mw psrr1 d.c. power supply rejection ratio change in full scale error with change in v a from 1.8v to 2.0v 30 db psrr2 a.c. power supply rejection ratio 248 mhz, 50mv p-p riding on v a 51 db ac electrical characteristics f clk1 maximum input clock frequency normal mode (non des) or des mode 800 500 mhz (min) f clk2 minimum input clock frequency normal mode (non des) 200 mhz f clk2 minimum input clock frequency des mode 450 mhz input clock duty cycle 200 mhz input clock frequency 800 mhz (normal mode) (note 12) 50 20 80 % (min) % (max) input clock duty cycle 450 mhz input clock frequency 800 mhz (des mode) (note 12) 50 20 80 % (min) % (max) t cl input clock low time (note 12) 500 400 ps (min) t ch input clock high time (note 12) 500 400 ps (min) adc08d500 www.national.com 10
converter electrical characteristics (continued) the following specifications apply after calibration for v a =v dr = +1.9v dc , outv = 1.9v, v in fsr (a.c. coupled) = differential 870mv p-p ,c l = 10 pf, differential, a.c. coupled sinewave input clock, f clk = 500 mhz at 0.5v p-p with 50% duty cycle, v bg = floating, non-extended control mode, sdr mode, r ext = 3300 ? 0.1%, analog signal source impedance = 100 ? differen- tial. boldface limits apply for t a =t min to t max . all other limits t a = 25?c, unless otherwise noted. (notes 6, 7) symbol parameter conditions typical (note 8) limits (note 8) units (limits) ac electrical characteristics dclk duty cycle (note 12) 50 45 55 % (min) % (max) t rs reset setup time (note 12) 150 ps t rh reset hold time (note 12) 250 ps t sd syncronizing edge to dclk output delay f clkin = 500 mhz f clkin = 200 mhz 3.53 3.85 ns t rpw reset pulse width (note 11) 4 clock cycles (min) t lht differential low to high transition time 10% to 90%, c l = 2.5 pf 250 ps t hlt differential high to low transition time 10% to 90%, c l = 2.5 pf 250 ps t osk dclk to data output skew 50% of dclk transition to 50% of data transition, sdr mode and ddr mode, 0? dclk (note 12) 50 ps (max) t su data to dclk set-up time ddr mode, 90? dclk (note 12) 2 ns t h dclk to data hold time ddr mode, 90? dclk (note 12) 2 ns t ad sampling (aperture) delay input clk+ fall to acquisition of data 1.3 ns t aj aperture jitter 0.4 ps rms t od input clock to data output delay (in addition to pipeline delay) 50% of input clock transition to 50% of data transition 3.1 ns pipeline delay (latency) (notes 11, 14) di outputs 13 clock cycles did outputs 14 dq outputs normal mode 13 des mode 13.5 dqd outputs normal mode 14 des mode 14.5 over range recovery time differential v in step from 1.2v to 0v to get accurate conversion 1 input clock cycle t wu pd low to rated accuracy conversion (wake-up time) 500 ns f sclk serial clock frequency (note 12) 100 mhz t ssu data to serial clock setup time (note 12) 2.5 ns (min) t sh data to serial clock hold time (note 12) 1 ns (min) serial clock low time 4 ns (min) serial clock high time 4 ns (min) t cal calibration cycle time 1.4 x 10 5 clock cycles t cal_l cal pin low time see figure 9 (note 11) 80 clock cycles (min) t cal_h cal pin high time see figure 9 (note 11) 80 clock cycles (min) t caldly calibration delay determined by pin 127 see section 1.1.1, figure 9 , (note 15) 2 25 clock cycles (min) adc08d500 www.national.com 11
converter electrical characteristics (continued) the following specifications apply after calibration for v a =v dr = +1.9v dc , outv = 1.9v, v in fsr (a.c. coupled) = differential 870mv p-p ,c l = 10 pf, differential, a.c. coupled sinewave input clock, f clk = 500 mhz at 0.5v p-p with 50% duty cycle, v bg = floating, non-extended control mode, sdr mode, r ext = 3300 ? 0.1%, analog signal source impedance = 100 ? differen- tial. boldface limits apply for t a =t min to t max . all other limits t a = 25?c, unless otherwise noted. (notes 6, 7) symbol parameter conditions typical (note 8) limits (note 8) units (limits) ac electrical characteristics t caldly calibration delay determined by pin 127 see section 1.1.1, figure 9 , (note 15) 2 31 clock cycles (max) note 1: absolute maximum ratings indicate limits beyond which damage to the device may occur. there is no guarantee of operation at the absolute maximum ratings. operating ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. for guarantee d specifications and test conditions, see the electrical characteristics. the guaranteed specifications apply only for the test conditions listed. some performance ch aracteristics may degrade when the device is not operated under the listed test conditions. note 2: all voltages are measured with respect to gnd = dr gnd = 0v, unless otherwise specified. note 3: when the input voltage at any pin exceeds the power supply limits (that is, less than gnd or greater than v a ), the current at that pin should be limited to 25 ma. the 50 ma maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 ma to t wo. this limit is not placed upon the power, ground and digital output pins. note 4: human body model is 100 pf capacitor discharged through a 1.5 k ? resistor. machine model is 220 pf discharged through zero ohms. note 5: see an-450, ?urface mounting methods and their effect on product reliability? note 6: the analog inputs are protected as shown below. input voltage magnitudes beyond the absolute maximum ratings may damage this device. 20121404 note 7: to guarantee accuracy, it is required that v a and v dr be well bypassed. each supply pin must be decoupled with separate bypass capacitors. additionally, achieving rated performance requires that the backside exposed pad be well grounded. note 8: typical figures are at t a = 25?c, and represent most likely parametric norms. test limits are guaranteed to nationals aoql (average outgoing quality level). note 9: calculation of full-scale error for this device assumes that the actual reference voltage is exactly its nominal value. full-scale error for this dev ice, therefore, is a combination of full-scale error and reference voltage error. see transfer characteristic figure 2 . for relationship between gain error and full-scale error, see specification definitions for gain error. note 10: the analog and clock input capacitances are die capacitances only. additional package capacitances of 0.65 pf differential and 0.95 pf each pin to gro und are isolated from the die capacitances by lead and bond wire inductances. note 11: this parameter is guaranteed by design and is not tested in production. note 12: this parameter is guaranteed by design and/or characterization and is not tested in production. note 13: the digital control pin capacitances are die capacitances only. additional package capacitance of 1.6 pf each pin to ground are isolated from the die capacitances by lead and bond wire inductances. note 14: each of the two converters of the adc08d500 has two lvds output buses, which each clock data out at one half the sample rate. the data at each bus is clocked out at one half the sample rate. the second bus (d0 through d7) has a pipeline latency that is one clock cycle less than the latency of the first b us (dd0 through dd7) note 15: tying v bg to the supply rail will increase the output offset voltage (v os ) by 400mv (typical), as shown in the v os specification above. tying v bg to the supply rail will also affect the differential lvds output voltage (v od ), causing it to increase by 40mv (typical). adc08d500 www.national.com 12
specification definitions aperture (sampling) delay is that time required after the fall of the clock input for the sampling switch to open. the sample/hold circuit effectively stops capturing the input sig- nal and goes into the ?old mode the aperture delay time (t ad ) after the clock goes low. aperture jitter (t aj ) is the variation in aperture delay from sample to sample. aperture jitter shows up as input noise. bit error rate (b.e.r.) is the probability of error and is defined as the probable number of errors per unit of time divided by the number of bits seen in that amount of time. a b.e.r. of 10 -18 corresponds to a statistical error in one bit about every four (4) years. clock duty cycle is the ratio of the time that the clock wave form is at a logic high to the total time of one clock period. differential non-linearity (dnl) is the measure of the maximum deviation from the ideal step size of 1 lsb. measured at 500 msps with a ramp input. effective number of bits (enob, or effective bits) is another method of specifying signal-to-noise and distortion ratio, or sinad. enob is defined as (sinad ? 1.76) / 6.02 and says that the converter is equivalent to a perfect adc of this (enob) number of bits. full power bandwidth (fpbw) is a measure of the frequency at which the reconstructed output fundamental drops 3 db below its low frequency value for a full scale input. gain error is the deviation from the ideal slope of the transfer function. it can be calculated from offset and full- scale errors: positive gain error = offset error ? positive full-scale error negative gain error = ?(offset error ? negative full- scale error) gain error = negative full-scale error ? positive full- scale error = positive gain error + negative gain error integral non-linearity (inl) is a measure of the deviation of each individual code from a straight line through the input to output transfer function. the deviation of any given code from this straight line is measured from the center of that code value. the best fit method is used. intermodulation distortion (imd) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the adc input at the same time. it is defined as the ratio of the power in the second and third order intermodulation products to the power in one of the original frequencies. imd is usually expressed in dbfs. lsb (least significant bit) is the bit that has the smallest value or weight of all bits. this value is v fs /2 n where v fs is the differential full-scale amplitude of 650 mv or 870 mv as set by the fsr input and "n" is the adc resolution in bits, which is 8 for the adc08d500. lvds differential output voltage (v od ) is the absolute value of the difference between the v d +&v d - outputs; each measured with respect to ground. lvds output offset voltage (v os ) is the midpoint between the d+ and d- pins output voltage; ie., [(v d +) +( v d -)]/2. missing codes are those output codes that are skipped and will never appear at the adc outputs. these codes cannot be reached with any input value. msb (most significant bit) is the bit that has the largest value or weight. its value is one half of full scale. negative full-scale error (nfse) is a measure of how far the last code transition is from the ideal 1/2 lsb above a differential ?870 mv with the fsr pin high, or 1/2 lsb above a differential ?650 mv with the fsr pin low. for the adc08d500 the reference voltage is assumed to be ideal, so this error is a combination of full-scale error and reference voltage error. offset error (v off ) is a measure of how far the mid- scale point is from the ideal zero voltage differential input. offset error = actual input causing average of 8k samples to result in an average code of 127.5. output delay (t od ) is the time delay after the falling edge of dclk before the data update is present at the output pins. over-range recovery time is the time required after the differential input voltages goes from 1.2v to 0v for the converter to recover and make a conversion with its rated accuracy. pipeline delay (latency) is the number of clock cycles between initiation of conversion and when that data is pre- sented to the output driver stage. new data is available at every clock cycle, but the data lags the conversion by the pipeline delay plus the t od . positive full-scale error (pfse) is a measure of how far the last code transition is from the ideal 1-1/2 lsb below a differential +870 mv with the fsr pin high, or 1-1/2 lsb below a differential +650 mv with the fsr pin low. for the adc08d500 the reference voltage is assumed to be ideal, so this error is a combination of full-scale error and reference voltage error. power supply rejection ratio (psrr) can be one of two specifications. psrr1 (dc psrr) is the ratio of the change in full-scale error that results from a power supply voltage change from 1.8v to 2.0v. psrr2 (ac psrr) is a measure of how well an a.c. signal riding upon the power supply is rejected from the output and is measured with a 248 mhz, 50 mv p-p signal riding upon the power supply. it is the ratio of the output amplitude of that signal at the output to its amplitude on the power supply pin. psrr is expressed in db. signal to noise ratio (snr) is the ratio, expressed in db, of the rms value of the input signal at the output to the 20121446 figure 1. adc08d500 www.national.com 13
specification definitions (continued) rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or d.c. signal to noise plus distortion (s/(n+d) or si- nad) is the ratio, expressed in db, of the rms value of the input signal at the output to the rms value of all of the other spectral components below half the clock frequency, includ- ing harmonics but excluding d.c. spurious-free dynamic range (sfdr) is the differ- ence, expressed in db, between the rms values of the input signal at the output and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that is not present at the input, excluding d.c. total harmonic distortion (thd) is the ratio ex- pressed in db, of the rms total of the first nine harmonic levels at the output to the level of the fundamental at the output. thd is calculated as where a f1 is the rms power of the fundamental (output) frequency and a f2 through a f10 are the rms power of the first 9 harmonic frequencies in the output spectrum. second harmonic distortion (2nd harm) is the differ- ence, expressed in db, between the rms power in the input frequency seen at the output and the power in its 2nd harmonic level at the output. third harmonic distortion (3rd harm) is the difference expressed in db between the rms power in the input fre- quency seen at the output and the power in its 3rd harmonic level at the output. transfer characteristic 20121422 figure 2. input / output transfer characteristic adc08d500 www.national.com 14
timing diagrams 20121414 figure 3. adc08d500 timing sdr clocking 20121459 figure 4. adc08d500 timing ddr clocking adc08d500 www.national.com 15
timing diagrams (continued) 20121419 figure 5. serial interface timing 20121420 figure 6. clock reset timing in ddr mode 20121423 figure 7. clock reset timing in sdr mode with outedge low adc08d500 www.national.com 16
timing diagrams (continued) 20121424 figure 8. clock reset timing in sdr mode with outedge high 20121425 figure 9. self calibration and on-command calibration timing adc08d500 www.national.com 17
1.0 functional description the adc08d500 is a versatile a/d converter with an inno- vative architecture permitting very high speed operation. the controls available ease the application of the device to circuit solutions. optimum performance requires adherence to the provisions discussed here and in the applications informa- tion section. while it is generally poor practice to allow an active pin to float, pins 4, 14 and 127 of the adc08d500 are designed to be left floating without jeopardy. in all discussions throughout this data sheet, whenever a function is called by allowing a pin to float, connecting that pin to a potential of one half the v a supply voltage will have the same effect as allowing it to float. 1.1 overview the adc08d500 uses a calibrated folding and interpolating architecture that achieves over 7.5 effective bits. the use of folding amplifiers greatly reduces the number of comparators and power consumption. interpolation reduces the number of front-end amplifiers required, minimizing the load on the input signal and further reducing power requirements. in addition to other things, on-chip calibration reduces the inl bow often seen with folding architectures. the result is an extremely fast, high performance, low power converter. the analog input signal that is within the converters input voltage range is digitized to eight bits at speeds of 200 msps to 500 msps, typical. differential input voltages be- low negative full-scale will cause the output word to consist of all zeroes. differential input voltages above positive full- scale will cause the output word to consist of all ones. either of these conditions at either the "i" or "q" input will cause the or (out of range) output to be activated. this single or output indicates when the output code from one or both of the channels is below negative full scale or above positive full scale. each of the two converters has a 1:2 demultiplexer that feeds two lvds output buses. the data on these buses provide an output word rate on each bus at half the adc sampling rate and must be interleaved by the user to provide output words at the full conversion rate. the output levels may be selected to be normal or reduced. using reduced levels saves power but could result in erro- neous data capture of some or all of the bits, especially at higher sample rates and in marginally designed systems. 1.1.1 self-calibration a self-calibration is performed upon power-up and can also be invoked by the user upon command. calibration trims the 100 ? analog input differential termination resistor and mini- mizes full-scale error, offset error, dnl and inl, resulting in maximizing snr, thd, sinad (sndr) and enob. internal bias currents are also set with the calibration process. all of this is true whether the calibration is performed upon power up or is performed upon command. running the self calibra- tion is an important part of this chips functionality and is required in order to obtain adequate performance. in addi- tion to the requirement to be run at power-up, self calibration must be re-run whenever the sense of the fsr pin is changed. for best performance, we recommend that self calibration be run 20 seconds or more after application of power and whenever the operating temperature changes significantly, according to the particular system design re- quirements. see section 2.4.2.2 for more information. cali- bration can not be initiated or run while the device is in the power-down mode. see section 1.7 for information on the interaction between power down and calibration. during the calibration process, the input termination resistor is trimmed to a value that is equal to r ext / 33. this external resistor is located between pin 32 and ground. r ext must be 3300 ? 0.1%. with this value, the input termination resistor is trimmed to be 100 ? . because r ext is also used to set the proper current for the track and hold amplifier, for the preamplifiers and for the comparators, other values of r ext should not be used. in normal operation, calibration is per- formed just after application of power and whenever a valid calibration command is given, which is holding the cal pin low for at least 80 clock cycles, then hold it high for at least another 80 clock cycles. the time taken by the calibration procedure is specified in the a.c. characteristics table. holding the cal pin high upon power up will prevent the calibration process from running until the cal pin experi- ences the above-mentioned 80 clock cycles low followed by 80 clock cycles high. caldly (pin 127) is used to select one of two delay times after the application of power to the start of calibration. this calibration delay is 2 25 clock cycles (about 67.2 ms at 500 msps) with caldly low, or 2 31 clock cycles (about 4.3 sec- onds at 500 msps) with caldly high. these delay values allow the power supply to come up and stabilize before calibration takes place. if the pd pin is high upon power-up, the calibration delay counter will be disabled until the pd pin is brought low. therefore, holding the pd pin high during power up will further delay the start of the power-up calibra- tion cycle. the best setting of the caldly pin depends upon the power-on settling time of the power supply. the calrun output is high whenever the calibration proce- dure is running. this is true whether the calibration is done at power-up or on-command. 1.1.2 acquiring the input data is acquired at the falling edge of clk+ (pin 18) and the digital equivalent of that data is available at the digital out- puts 13 clock cycles later for the di and dq output buses and 14 clock cycles later for the did and dqd output buses. there is an additional internal delay called t od before the data is available at the outputs. see the timing diagram. the adc08d500 will convert as long as the clock signal is present. the fully differential comparator design and the innovative design of the sample-and-hold amplifier, together with self calibration, enables a very flat sinad/enob re- sponse beyond 500 mhz. the adc08d500 output data sig- naling is lvds and the output format is offset binary. 1.1.3 control modes much of the user control can be accomplished with several control pins that are provided. examples include initiation of the calibration cycle, power down mode and full scale range setting. however, the adc08d500 also provides an ex- tended control mode whereby a serial interface is used to access register-based control of several advanced features. the extended control mode is not intended to be enabled and disabled dynamically. rather, the user is expected to employ either the normal control mode or the extended control mode at all times. when the device is in the ex- tended control mode, pin-based control of several features is replaced with register-based control and those pin-based controls are disabled. these pins are outv (pin 3), outedge/ ddr (pin 4), fsr (pin 14) and caldly/des (pin 127). see section 1.2 for details on the extended control mode. adc08d500 www.national.com 18
1.0 functional description (continued) 1.1.4 the analog inputs the adc08d500 must be driven with a differential input signal. operation with a single-ended signal is not recom- mended. it is important that the inputs either be a.c. coupled to the inputs with the v cmo pin grounded or d.c. coupled with the v cmo pin not grounded and an input common mode voltage equal to the v cmo output. two full-scale range settings are provided with pin 14 (fsr). a high on pin 14 causes an input full-scale range setting of 870 mv p-p , while grounding pin 14 causes an input full-scale range setting of 650 mv p-p . the full-scale range setting operates equally on both adcs. in the extended control mode, the full-scale input range can be set to values between 560 mv p-p and 840 mv p-p through a serial interface. see section 2.2 1.1.5 clocking the adc08d500 must be driven with an a.c. coupled, differ- ential clock signal. section 2.3 describes the use of the clock input pins. a differential lvds output clock is available for use in latching the adc output data into whatever receives that data. the adc08d500 offers options for input and output clocking. these options include a choice of dual edge sampling (des) or interleaved mode where the adc08d500 performs as a single device converting at twice the input clock rate and a choice of which dclk edge the output data transitions on and choice of single data rate (sdr) or double data rate (ddr) outputs. the adc08d500 also has the option to use a duty cycle corrected clock receiver as part of the input clock circuit. this feature is enabled by default and provides improved adc clocking, especially in the dual-edge sampling mode (des). this circuitry allows the adc to be clocked with a signal source having a duty cycle ratio of 80 / 20 % (worst case) for both the normal and the dual edge sampling modes. 1.1.5.1 dual-edge sampling the des mode allows one of the adc08d500s inputs (i or q channel) to be sampled by both adcs. one adc samples the input on the positive edge of the input clock and the other adc samples the same input on the other edge of the input clock. a single input is thus sampled twice per clock cycle, resulting in an overall sample rate of twice the input clock frequency, or 1 gsps with a 500 mhz clock. in this mode the outputs are interleaved such that the data is effectively demultiplexed 1:4. since the sample rate is doubled, each of the 4 output buses have a 250 msps output rate with a 500 mhz input clock. all data is available in parallel. the four bytes of parallel data that is output with each clock is in the following sampling order, from the earli- est to the latest: dqd, did, dq, di. table 1 indicates what the outputs represent for the various sampling possibilities. in the non-extended mode of operation only the "i" input can be sampled in the des mode. in the extended mode of operation the user can select which input is sampled. the adc08d500 also includes an automatic clock phase background calibration feature which can be used in des mode to automatically and continuously adjust the clock phase of the i and q channel. this feature removes the need to adjust the clock phase setting manually and provides optimal dual-edge sampling enob performance. important note: the background calibration feature in des mode does not replace the requirement for on- command calibration which should be run before entering des mode, or if a large swing in ambient temperature is experienced by the device. table 1. input channel samples produced at data outputs data outputs (always sourced with respect to fall of dclk) normal sampling mode dual-edge sampling mode i-channel selected q-channel selected * di "i" input sampled with fall of clk 13 cycles earlier. "i" input sampled with fall of clk 13 cycles earlier. "q" input sampled with fall of clk 13 cycles earlier. did "i" input sampled with fall of clk 14 cycles earlier. "i" input sampled with fall of clk 14 cycles earlier. "q" input sampled with fall of clk 14 cycles earlier. dq "q" input sampled with fall of clk 13 cycles earlier. "i" input sampled with rise of clk 13.5 cycles earlier. "q" input sampled with rise of clk 13.5 cycles earlier. dqd "q" input sampled with fall of clk 14 cycles after being sampled. "i" input sampled with rise of clk 14.5 cycles earlier. "q" input sampled with rise of clk 14.5 cycles earlier. * note that, in the dual-edge sampling (des) mode, the "q" channel input can only be selected for sampling in the extended control mode. 1.1.5.2 outedge setting to help ease data capture in the sdr mode, the output data may be caused to transition on either the positive or the negative edge of the output data clock (dclk). this is chosen with the outedge input (pin 4). a high on the out- edge input causes the output data to transition on the rising edge of dclk, while grounding this input causes the output to transition on the falling edge of dclk. see section 2.4.3. 1.1.5.3 double data rate a choice of single data rate (sdr) or double data rate (ddr) output is offered. with single data rate the clock frequency is the same as the data rate of the two output buses. with adc08d500 www.national.com 19
1.0 functional description (continued) double data rate the clock frequency is half the data rate and data is sent to the outputs on both dclk edges. ddr clocking is enabled in non-extended control mode by allow- ing pin 4 to float. 1.1.6 the lvds outputs the data outputs, the out of range (or) and dclk, are lvds. output current sources provide 3 ma of output current to a differential 100 ohm load when the outv input (pin 14) is high or 2.2 ma when the outv input is low. for short lvds lines and low noise systems, satisfactory performance may be realized with the outv input low, which results in lower power consumption. if the lvds lines are long and/or the system in which the adc08d500 is used is noisy, it may be necessary to tie the outv pin high. the lvds data output have a typical common mode voltage of 800mv when the v bg pin is unconnected and floating. this common mode voltage can be increased to 1.2v by tying the v bg pin to v a if a higher common mode is required. important note: tying the v bg pin to v a will also in- crease the differential lvds output voltage by upto 40mv. 1.1.7 power down the adc08d500 is in the active state when the power down pin (pd) is low. when the pd pin is high, the device is in the power down mode, where the output pins hold the last conversion before the pd pin went high and the device power consumption is reduced to a minimual level. a high on the pdq pin will power down the "q" channel and leave the "i" channel active. there is no provision to power down the "i" channel independently of the "q" channel. upon return to normal operation, the pipeline will contain meaningless in- formation. if the pd input is brought high while a calibration is running, the device will not go into power down until the calibration sequence is complete. however, if power is applied and pd is already high, the device will not begin the calibration sequence until the pd input goes low. if a manual calibration is requested while the device is powered down, the calibra- tion will not begin at all. that is, the manual calibration input is completely ignored in the power down state. calibration will function with the "q" channel powered down, but that channel will not be calibrated if pdq is high. if the "q" channel is subsequently to be used, it is necessary to per- form a calibration after pdq is brought low. 1.2 normal/extended control the adc08d500 may be operated in one of two modes. in the simpler "normal" control mode, the user affects available configuration and control of the device through several con- trol pins. the "extended control mode" provides additional configuration and control options through a serial interface and a set of 8 registers. the two control modes are selected with pin 14 (fsr/ece: extended control enable). the choice of control modes is required to be a fixed selection and is not intended to be switched dynamically while the device is operational. table 2 shows how several of the device features are af- fected by the control mode chosen. table 2. features and modes feature normal control mode extended control mode sdr or ddr clocking selected with pin 4 selected with de bit in the configuration register ddr clock phase not selectable (0? phase only) selected with dcp bit in the configuration register. see section 1.4 sdr data transitions with rising or falling dclk edge selected with pin 4 selected with the oe bit in the configuration register lvds output level selected with pin 3 selected with the ov bit in the configuration register power-on calibration delay delay selected with pin 127 short delay only. full-scale range options (650 mv p-p or 870 mv p-p ) selected with pin 14. selected range applies to both channels. up to 512 step adjustments over a nominal range of 560 mv to 840 mv. separate range selected for i- and q-channels. selected using registers 3h and bh input offset adjust not possible separate 45 mv adjustments in 512 steps for each channel using registers 2h and ah dual edge sampling selection enabled with pin 127 enabled through des enable register dual edge sampling input channel selection only i-channel input can be used either i- or q-channel input may be sampled by both adcs des sampling clock adjustment the clock phase is adjusted automatically automatic clock phase control can be selected by setting bit 14 in the des enable register (dh). the clock phase can also be adjusted manually through the coarse & fine registers eh and fh adc08d500 www.national.com 20
1.0 functional description (continued) the default state of the extended control mode is set upon power-on reset (internally performed by the device) and is shown in table 3 . table 3. extended control mode operation (pin 14 floating) feature extended control mode default state sdr or ddr clocking ddr clocking ddr clock phase data changes with dclk edge (0? phase) lvds output amplitude normal amplitude (710 mv p-p ) calibration delay short delay full-scale range 700 mv nominal for both channels input offset adjust no adjustment for either channel dual edge sampling (des) not enabled 1.3 the serial interface the 3-pin serial interface is enabled only when the device is in the extended control mode. the pins of this interface are serial clock (sclk), serial data (sdata) and serial inter- face chip select (scs) eight write only registers are acces- sible through this serial interface. scs: this signal should be asserted low while accessing a register through the serial interface. setup and hold times with respect to the sclk must be observed. sclk : serial data input is accepted with the rising edge of this signal. sdata: each register access requires a specific 32-bit pat- tern at this input. this pattern consists of a header, register address and register value. the data is shifted in msb first. setup and hold times with respect to the sclk must be observed. see the timing diagram. each register access consists of 32 bits, as shown in figure 5 of the timing diagrams. the fixed header pattern is 0000 0000 0001 (eleven zeros followed by a 1). the loading sequence is such that a 0b is loaded first. these 12 bits form the header. the next 4 bits are the address of the register that is to be written to and the last 16 bits are the data written to the addressed register. the addresses of the various registers are indicated in table 4 . refer to the register description (section 1.4) for informa- tion on the data to be written to the registers. subsequent register accesses may be performed immedi- ately, starting with the 33rd sclk. this means that the scs input does not have to be de-asserted and asserted again between register addresses. it is possible, although not rec- ommended, to keep the scs input permanently enabled (at a logic low) when using extended control. important note: the serial interface should not be used when calibrating the adc. doing so will impair the performance of the device until it is re-calibrated correctly. programming the serial registers will also reduce dynamic performance of the adc for the duration of the register access time. table 4. register addresses 4-bit address loading sequence: a3 loaded after h0, a0 loaded last a3 a2 a1 a0 hex register addressed 0 0 0 0 0h reserved 0 0 0 1 1h configuration 0 0 1 0 2h "i" ch offset 0 0 1 1 3h "i" ch full-scale voltage adjust 0 1 0 0 4h reserved 0 1 0 1 5h reserved 0 1 1 0 6h reserved 0 1 1 1 7h reserved 1 0 0 0 8h reserved 1 0 0 1 9h reserved 1 0 1 0 ah "q" ch offset 1 0 1 1 bh "q" ch full-scale voltage adjust 1 1 0 0 ch reserved 1 1 0 1 dh des enable 1 1 1 0 eh des coarse adjust 1 1 1 1 fh des fine adjust 1.4 register description eight write-only registers provide several control and con- figuration options in the extended control mode. these reg- isters have no effect when the device is in the normal control mode. each register description below also shows the power-on reset (por) state of each control bit. configuration register addr: 1h (0001b) w only (0xb2ff) d15 d14 d13 d12 d11 d10 d9 d8 1 0 1 dcs dcp nde ov oe d7 d6 d5 d4 d3 d2 d1 d0 11111111 bit 15 must be set to 1b bit 14 must be set to 0b bit 13 must be set to 1b bit 12 dcs: duty cycle stabilizer. when this bit is set to 1b, a duty cycle stabilization circuit is applied to the clock input. when this bit is set to 0b the stabilization circuit is disbaled. adc08d500 www.national.com 21
1.0 functional description (continued) bit 11 dcp: ddr clock phase. this bit only has an effect in the ddr mode. when this bit is set to 0b, the dclk edges are time-aligned with the data bus edges ("0? phase"). when this bit is set to 1b, the dclk edges are placed in the middle of the data bit-cells ("90? phase"), using the one-half speed dclk shown in figure 4 as the phase reference. por state: 0b bit 10 nde: ddr enable. when this bit is set to 0b, data bus clocking follows the ddr (dual data rate) mode whereby a data word is output with each rising and falling edge of dclk. when this bit is set to a 1b, data bus clocking follows the sdr (single data rate) mode whereby each data word is output with either the rising or falling edge of dclk , as determined by the outedge bit. por state: 0b bit 9 ov: output voltage. this bit determines the lvds outputs voltage amplitude and has the same function as the outv pin that is used in the normal control mode. when this bit is set to 1b, the standard output amplitude of 710 mv p-p is used. when this bit is set to 0b, the reduced output amplitude of 510 mv p-p is used. por state: 1b bit 8 oe: output edge. this bit selects the dclk edge with which the data words transition in the sdr mode and has the same effect as the outedge pin in the normal control mode. when this bit is 1b, the data outputs change with the rising edge of dclk+. when this bit is 0b, the data output change with the falling edge of dclk+. por state: 0b bits 7:0 must be set to 1b. i-channel offset addr: 2h (0010b) w only (0x007f) d15 d14 d13 d12 d11 d10 d9 d8 (msb) offset value (lsb) d7 d6 d5 d4 d3 d2 d1 d0 sign 1111111 bits 15:8 offset value. the input offset of the i-channel adc is adjusted linearly and monotonically by the value in this field. 00h provides a nominal zero offset, while ffh provides a nominal 45 mv of offset. thus, each code step provides 0.176 mv of offset. por state: 0000 0000b bit 7 sign bit. 0b gives positive offset, 1b gives negative offset. por state: 0b bit 6:0 must be set to 1b adc08d500 www.national.com 22
1.0 functional description (continued) i-channel full-scale voltage adjust addr: 3h (0011b) w only (0x807f) d15 d14 d13 d12 d11 d10 d9 d8 (msb) adjust value d7 d6 d5 d4 d3 d2 d1 d0 (lsb) 1111111 bit 15:7 full scale voltage adjust value. the input full-scale voltage of the i-channel adc is adjusted linearly and monotonically from the nominal 700 mv p-p differential by the value in this field. 0000 0000 0 560mv p-p 1000 0000 0 700mv p-p 1111 1111 1 840mv p-p for best performance, it is recommended that the value in this field be limited to the range of 0110 0000 0b to 1110 0000 0b. i.e., limit the amount of adjustment to 15%. the remaining 5% headroom allows for the adc? own full scale variation .a gain adjustment does not require adc re-calibration. por state: 1000 0000 0b (no adjustment) bits 6:0 must be set to 1b q-channel offset addr: ah (1010b) w only (0x007f) d15 d14 d13 d12 d11 d10 d9 d8 (msb) offset value (lsb) d7 d6 d5 d4 d3 d2 d1 d0 sign 1111111 bit 15:8 offset value. the input offset of the q-channel adc is adjusted linearly and monotonically by the value in this field. 00h provides a nominal zero offset, while ffh provides a nominal 45 mv of offset. thus, each code step provides about 0.176 mv of offset. por state: 0000 0000b bit 7 sign bit. 0b gives positive offset, 1b gives negative offset. por state: 0b bit 6:0 must be set to 1b adc08d500 www.national.com 23
1.0 functional description (continued) q-channel full-scale voltage adjust addr: bh (1011b) w only (0x807f) d15 d14 d13 d12 d11 d10 d9 d8 (msb) adjust value d7 d6 d5 d4 d3 d2 d1 d0 (lsb) 1111111 bit 15:7 full scale voltage adjust value. the input full-scale voltage of the q-channel adc is adjusted linearly and monotonically from the nominal 700 mv p-p differential by the value in this field. 0000 0000 0 560mv p-p 1000 0000 0 700mv p-p 1111 1111 1 840mv p-p for best performance, it is recommended that the value in this field be limited to the range of 0110 0000 0b to 1110 0000 0b. i.e., limit the amount of adjustment to 15%. the remaining 5% headroom allows for the adc? own full scale variation .a gain adjustment does not require adc re-calibration. por state: 1000 0000 0b (no adjustment) bits 6:0 must be set to 1b des enable addr: dh (1101b) w only (0x3fff) d15 d14 d13 d12 d11 d10 d9 d8 denacp111111 d7 d6 d5 d4 d3 d2 d1 d0 11111111 bit 15 des enable. setting this bit to 1b enables the dual edge sampling mode. in this mode the adcs in this device are used to sample and convert the same analog input in a time-interleaved manner, accomplishing a sampling rate of twice the input clock rate. when this bit is set to 0b, the device operates in the normal dual channel mode. por state: 0b bit 14 automatic clock phase (acp) control. setting this bit to 1b enables the automatic clock phase control. in this mode the des coarse and fine manual controls are disabled. a phase detection circuit continually adjusts the i and q sampling edges to be 180 degrees out of phase. when this bit is set to 0b, the sample (input) clock delay between the i and q channels is set manually using the des coarse and fine adjust registers. (see section 2.4.5 for important application information) using the acp control option is recommended over the manual des settings . por state: 0b bits 13:0 must be set to 1b des coarse adjust addr: eh (1110b) w only (0x07ff) d15 d14 d13 d12 d11 d10 d9 d8 is ads cam 1 1 1 d7 d6 d5 d4 d3 d2 d1 d0 11111111 bit 15 input select. when this bit is set to 0b the "i" input is operated upon by both adcs. when this bit is set to 1b the "q" input is operated on by both adcs. por state: 0b bit 14 adjust direction select. when this bit is set to 0b, the programmed delays are applied to the "i" channel sample clock while the "q" channel sample clock remains fixed. when this bit is set to 1b, the programmed delays are applied to the "q" channel sample clock while the "i" channel sample clock remains fixed. por state: 0b bits 13:11 coarse adjust magnitude. each code value in this field delays either the "i" channel or the "q" channel sample clock (as determined by the ads bit) by approximately 20 picoseconds. a value of 000b in this field causes zero adjustment. por state: 000b bits 10:0 must be set to 1b adc08d500 www.national.com 24
1.0 functional description (continued) des fine adjust addr: fh ( 1111b) w only (0x007f) d15 d14 d13 d12 d11 d10 d9 d8 (msb) fam d7 d6 d5 d4 d3 d2 d1 d0 (lsb) 1111111 bits 15:7 fine adjust magnitude. each code value in this field delays either the "i" channel or the "q" channel sample clock (as determined by the ads bit of the des coarse adjust register) by approximately 0.1 ps. a value of 0000 0000 0b in this field causes zero adjustment. note that the amount of adjustment achieved with each code will vary with the device conditions as well as with the coarse adjustment value chosen. por state: 0000 0000 0b bit 6:0 must be set to 1b 1.4.1 note regarding extended mode offset correction when using the i or q channel offset adjust registers, the following information should be noted. for offset values of +0000 0000 and -0000 0000, the actual offset is not the same. by changing only the sign bit in this case, an offset step in the digital output code of about 1/10th of an lsb is experienced. this is shown more clearly in the figure below. 1.5 multiple adc synchronization the adc08d500 has the capability to precisely reset its sampling clock input to dclk output relationship as deter- mined by the user-supplied dclk_rst pulse. this allows multiple adcs in a system to have their dclk (and data) outputs transition at the same time with respect to the shared clk input that they all use for sampling. the dclk_rst signal must observe some timing require- ments that are shown in figure 6 , figure 7 , and figure 8 of the timing diagrams. the dclk_rst pulse must be of a minimum width and its deassertion edge must observe setup and hold times with respect to the clk input rising edge. these times are specified in the ac electrical characteris- tics table. the dclk_rst signal can be asserted asynchronous to the input clock if dclk_rst is asserted, the dclk output is held in a designated state. the state in which dclk is held during the reset period is determined by the mode of opera- tion (sdr/ddr) and the setting of the output edge configu- ration pin or bit. (refer to figure 6 , figure 8 , and figure 8 for the dclk reset condictions). therefore depending upon when the dclk_rst signal is asserted, there may be a narrow pulse on the dclk line during this reset event. when the dclk_rst signal is de-asserted in synchronization with the clk rising edge, the next clk falling edge synchronizes the dclk output with those of other adc08d500s in the system. the dclk output is enabled again after a constant delay which is equal to the clk input to dclk output delay (t ad ). the device always exhibits this delay characteristic in normal operation. the dclk-rst pin should not be brought high while the calibration process is running (while calrun is high). doing so could cause a digital glitch in the digital circuitry, resulting in corruption and invalidation of the calibration. 2.0 applications information 2.1 the reference voltage the voltage reference for the adc08d500 is derived from a 1.254v bandgap reference which is made available at pin 31, v bg for user convenience and has an output current capability of 100 ? and should be buffered if more current than this is required. the internal bandgap-derived reference voltage has a nomi- nal value of 650 mv or 870 mv, as determined by the fsr pin and described in section 1.1.4. there is no provision for the use of an external reference voltage, but the full-scale input voltage can be adjusted through a configuration register in the extended control mode, as explained in section 1.2. differential input signals up to the chosen full-scale level will be digitized to 8 bits. signal excursions beyond the full-scale range will be clipped at the output. these large signal excur- sions will also activate the or output for the time that the signal is out of range. see section 2.2.2. one extra feature of the v bg pin is that it can be used to raise the common mode voltage level of the lvds outputs. the output offset voltage (v os ) is typically 800mv when the v bg pin is used as an output or left unconnected. to raise the lvds offset voltage to a typical value of 1200mv the v bg pin can be connected directly to the supply rails. 2.2 the analog input the analog input is a differential one to which the signal source may be a.c. coupled or d.c. coupled. the full-scale input range is selected with the fsr pin to be 650 mv p-p or 870 mv p-p , or can be adjusted to values between 560 mv p-p and 840 mv p-p in the extended control mode through the serial interface. for best performance, it is recommended that the full-scale range be kept between 595 mv p-p and 805 mv p-p in the extended control mode. table 5 gives the input to output relationship with the fsr pin high and the normal (non-extended) mode is used. with the fsr pin grounded, the millivolt values in table 5 are reduced to 75% of the values indicated. in the enhanced control mode, these values will be determined by the full scale range and offset settings in the control registers. 20121430 figure 10. extended mode offset behavior adc08d500 www.national.com 25
2.0 applications information (continued) table 5. differential input to output relationship (non-extended control mode, fsr high) v in +v in ? output code v cm ? 217.5mv v cm + 217.5mv 0000 0000 v cm ? 109mv v cm + 109mv 0100 0000 v cm v cm 0111 1111 / 1000 0000 v cm + 109 mv v cm ? 109mv 1100 0000 v cm + 217.5mv v cm ? 217.5mv 1111 1111 the buffered analog inputs simplify the task of driving these inputs and the rc pole that is generally used at sampling adc inputs is not required. if it is desired to use an amplifier circuit before the adc, use care in choosing an amplifier with adequate noise and distortion performance and adequate gain at the frequencies used for the application. note that a precise d.c. common mode voltage must be present at the adc inputs. this common mode voltage, v cmo , is provided on-chip when a.c. input coupling is used and the input signal is a.c. coupled to the adc. when the inputs are a.c. coupled, the v cmo output must be grounded, as shown in figure 11 . this causes the on-chip v cmo voltage to be connected to the inputs through on-chip 50k-ohm resistors. important note : an analog input channel that is not used (e.g. in des mode) should be left floating when the inputs are a.c. coupled. do not connect an unused analog input to ground. when the d.c. coupled mode is used, a common mode voltage must be provided at the differential inputs. this common mode voltage should track the v cmo output pin. note that the v cmo output potential will change with tem- perature. the common mode output of the driving device should track this change. important note: an analog input channel that is not used (e.g. in des mode) should be tied to the v cmo voltage when the inputs are d.c coupled. do not connect unused analog inputs to ground. full-scale distortion performance falls off rapidly as the input common mode voltage deviates from v cmo . this is a direct result of using a very low supply voltage to minimize power. keep the input common voltage within 50 mv of v cmo . performance is as good in the d.c. coupled mode as it is in the a.c. coupled mode, provided the input common mode voltage at both analog inputs remain within 50 mv of v cmo . if d.c. coupling is used, it is best to servo the input common mode voltage, using the v cmo pin, to maintain optimum performance. an example of this type of circuit is shown in figure 12 . one such circuit should be used in front of the v in + input and another in front of the v in ? input. in that figure, r d1 ,r d2 and r d3 are used to divide the v cmo potential so that, after being gained up by the amplifier, the input common mode voltage is equal to v cmo from the adc. r d1 and r d2 are split to allow the bypass capacitor to isolate the input signal from v cmo .r in ,r d2 and r d3 will divide the input signal, if nec- essary. capacitor "c" in figure 12 should be chosen to keep any component of the input signal from affecting v cmo . be sure that the current drawn from the v cmo output does not exceed 100 ?. the input impedance in the d.c. coupled mode (v cmo pin not grounded) consists of a precision 100 ? resistor between v in + and v in ? and a capacitance from each of these inputs to ground. in the a.c. coupled mode the input appears the same except there is also a resistor of 50k between each analog input pin and the v cmo potential. driving the inputs beyond full scale will result in a saturation or clipping of the reconstructed output. 2.2.1 handling single-ended input signals there is no provision for the adc08d500 to adequately process single-ended input signals. the best way to handle single-ended signals is to convert them to differential signals before presenting them to the adc. the easiest way to accomplish single-ended to differential signal conversion is with an appropriate balun-connected transformer, as shown in figure 13 . 20121444 figure 11. differential input drive 20121455 figure 12. example of servoing the analog input with v cmo 20121443 figure 13. single-ended to differential signal conversion with a balun-connected transformer adc08d500 www.national.com 26
2.0 applications information (continued) the 100 ohm external resistor placed accross the output terminals of the balun in parallel with the adc08d1000s on-chip 100 ohm resistor makes a 50 ohms differential impedance at the balun output. or, 25 ohms to virtual ground at each of the balun output terminals. looking into the balun, the source sees the impedance of the first coil in series with the impedance at the output of that coil. since the transformer has a 1:1 turns ratio, the imped- ance across the first coil is exactly the same as that at the output of the second coil, namely 25 ohms to virtual ground. so, the 25 ohms across the first coil in series with the 25 ohms at its output gives 50 ohms total impedance to match the source. 2.2.2 out of range (or) indication when the conversion result is clipped the out of range output is activated such that or+ goes high and or- goes low. this output is active as long as accurate data on either or both of the buses would be outside the range of 00h to ffh. 2.2.3 full-scale input range as with all a/d converters, the input range is determined by the value of the adcs reference voltage. the reference voltage of the adc08d500 is derived from an internal band- gap reference. the fsr pin controls the effective reference voltage of the adc08d500 such that the differential full-scale input range at the analog inputs is 870 mv p-p with the fsr pin high, or is 650 mv p-p with fsr pin low. best snr is obtained with fsr high, but better distortion and sfdr are obtained with the fsr pin low. 2.3 the clock inputs the adc08d500 has differential lvds clock inputs, clk+ and clk-, which must be driven with an a.c. coupled, differ- ential clock signal. although the adc08d500 is tested and its performance is guaranteed with a differential 500 mhz clock, it typically will function well with clock frequencies indicated in the electrical characteristics table. the clock inputs are internally terminated and biased. the clock signal must be capacitively coupled to the clock pins as indicated in figure 14 . operation up to the sample rates indicated in the electrical characteristics table is typically possible if the maximum ambient temperatures indicated are not exceeded. operat- ing at higher sample rates than indicated for the given am- bient temperature may result in reduced device reliability and product lifetime. this is because of the higher power consumption and die temperatures at high sample rates. important also for reliability is proper thermal management . see section 2.6.2. the differential clock line pair should have a characteristic impedance of 100 ? and be terminated at the clock source in that (100 ? ) characteristic impedance. the clock line should be as short and as direct as possible. the adc08d500 clock input is internally terminated with an untrimmed 100 ? resis- tor. insufficient clock levels will result in poor dynamic perfor- mance. excessively high clock levels could cause a change in the analog input offset voltage. to avoid these problems, keep the clock level within the range specified in the electri- cal characteristics table. the low and high times of the input clock signal can affect the performance of any a/d converter. the adc08d1000 features a duty cycle clock correction circuit which can main- tain performance over temperature even in des mode. the adc will meet its performance specification if the input clock high and low times are maintained within the range (20/80% ratio) as specified in the electrical characteristics table. high speed, high performance adcs such as the adc08d500 require a very stable clock signal with minimum phase noise or jitter. adc jitter requirements are defined by the adc resolution (number of bits), maximum adc input frequency and the input signal amplitude relative to the adc input full scale range. the maximum jitter (the sum of the jitter from all sources) allowed to prevent a jitter-induced reduction in snr is found to be t j(max) =(v in(p-p) /v infsr ) x (1/(2 (n+1) x xf in )) where t j(max) is the rms total of all jitter sources in seconds, v in(p-p) is the peak-to-peak analog input signal, v infsr is the full-scale range of the adc, "n" is the adc resolution in bits and f in is the maximum input frequency, in hertz, to the adc analog input. note that the maximum jitter described above is the arith- metic sum of the jitter from all sources, including that in the adc clock, that added by the system to the adc clock and input signals and that added by the adc itself. since the effective jitter added by the adc is beyond user control, the best the user can do is to keep the sum of the externally added clock jitter and the jitter added by the analog circuitry to the analog signal to a minimum. clock amplitudes above those specified in the electrical characteristics table may result in increased input offset voltage. this would cause the converter to produce an out- put code other than the expected 127/128 when both input pins are at the same potential. 2.4 control pins six control pins (without the use of the serial interface) provide a wide range of possibilities in the operation of the adc08d500 and facilitate its use. these control pins provide 20121447 figure 14. differential (lvds) clock connection adc08d500 www.national.com 27
2.0 applications information (continued) full-scale input range setting, self calibration, calibration delay, output edge synchronization choice, lvds output level choice and a power down feature. 2.4.1 full-scale input range setting the input full-scale range can be selected to be either 650 mv p-p or 870 mv p-p , as selected with the fsr control input (pin 14) in the normal mode of operation. in the extended control mode, the input full-scale range may be set to be anywhere from 560 mv p-p to 840 mv p-p . see section 2.2 for more information. 2.4.2 self calibration the adc08d500 self-calibration must be run to achieve specified performance. the calibration procedure is run upon power-up and can be run any time on command. the calibration procedure is exactly the same whether there is a clock present upon power up or if the clock begins some time after application of power. the calrun output indicator is high while a calibration is in progress. 2.4.2.1 power-on calibration power-on calibration begins after a time delay following the application of power. this time delay is determined by the setting of caldly, as described in the calibration delay sec- tion, below. the calibration process will be not be performed if the cal pin is high at power up. in this case, the calibration cycle will not begin until the on-command calibration conditions are met. the adc08d500 will function with the cal pin held high at power up, but no calibration will be done and perfor- mance will be impaired. a manual calibration, however, may be performed after powering up with the cal pin high. see on-command calibration section 2.4.2.2. the internal power-on calibration circuitry comes up in an unknown logic state. if the clock is not running at power up and the power on calibration circuitry is active, it will hold the analog circuitry in power down and the power consumption will typically be less than 200 mw. the power consumption will be normal after the clock starts. 2.4.2.2 on-command calibration an on-command calibration may be run at any time in nor- mal (non-des) mode only. do not run a calibration while operating the adc in auto des mode. if the adc is operating in auto des mode and a calibration cycle is required then the controlling application should bring the adc into normal (non des) mode before an on com- mand calibration is initiated. once calibration has completed, the adc can be put back into auto des mode. to initiate an on-command calibration, bring the cal pin high for a minimum of 80 input clock cycles after it has been low for a minimum of 80 input clock cycles. holding the cal pin high upon power up will prevent execution of power-on calibration until the cal pin is low for a minimum of 80 input clock cycles, then brought high for a minimum of another 80 input clock cycles. the calibration cycle will begin 80 input clock cycles after the cal pin is thus brought high. the calrun signal should be monitored to determine when the calibration cycle has completed. the minimum 80 input clock cycle sequences are required to ensure that random noise does not cause a calibration to begin when it is not desired. as mentioned in section 1.1.1 for best performance, a self calibration should be performed 20 seconds or more after power up and repeated when the operating temperature changes significantly according to the particular system performance requirements. enob drops slightly as junction temperature increases and executing a new self calibration cycle will essentially eliminate the change. 2.4.2.3 calibration delay the caldly input (pin 127) is used to select one of two delay times after the application of power to the start of calibration, as described in section 1.1.1. the calibration delay values allow the power supply to come up and stabilize before calibration takes place. with no delay or insufficient delay, calibration would begin before the power supply is stabilized at its operating value and result in non-optimal calibration coefficients. if the pd pin is high upon power-up, the calibra- tion delay counter will be disabled until the pd pin is brought low. therefore, holding the pd pin high during power up will further delay the start of the power-up calibration cycle. the best setting of the caldly pin depends upon the power-on settling time of the power supply. note that the calibration delay selection is not possible in the extended control mode and the short delay time is used. 2.4.3 output edge synchronization dclk signals are available to help latch the converter output data into external circuitry. the output data can be synchro- nized with either edge of these clock signals. that is, the output data transition can be set to occur with either the rising edge or the falling edge of the dclk signal, so that either edge of that clock signal can be used to latch the output data into the receiving circuit. when outedge (pin 4) is high, the output data is synchro- nized with (changes with) the rising edge of the dclk+ (pin 82). when outedge is low, the output data is synchronized with the falling edge of dclk+. at the very high speeds of which the adc08d500 is capable, slight differences in the lengths of the clock and data lines can mean the difference between successful and erroneous data capture. the outedge pin is used to capture data on the dclk edge that best suits the application circuit and layout. 2.4.4 lvds output level control the output level can be set to one of two levels with outv (pin3). the strength of the output drivers is greater with outv high. with outv low there is less power consumption in the output drivers, but the lower output level means decreased noise immunity. for short lvds lines and low noise systems, satisfactory performance may be realized with the fsr input low. if the lvds lines are long and/or the system in which the adc08d500 is used is noisy, it may be necessary to tie the fsr pin high. 2.4.5 dual edge sampling the dual edge sampling (des) feature causes one of the two input pairs to be routed to both adcs. the other input pair is deactivated. one of the adcs samples the input signal on one clock edge, the other samples the input signal on the other clock edge. the result is a 1:4 demultiplexed output with a sample rate that is twice the input clock fre- quency. adc08d500 www.national.com 28
2.0 applications information (continued) to use this feature in the non-enhanced control mode, allow pin 127 to float and the signal at the "i" channel input will be sampled by both converters. the calibration delay will then only be a short delay. in the enhanced control mode, either input may be used for dual edge sampling. see section 1.1.5.1. important notes: 1) for the extended control mode - when using the auto- matic clock phase control feature in dual edge sampling mode, it is important that the automatic phase control is disabled (set bit 14 of des enable register dh to 0) before the adc is powered up. not doing so may cause the device not to wakeup from the powerdown state. 2) for the non-extended control mode - when the adc08d1000 is powered up and des mode is required, ensure that pin 127 (caldly/des/scs) is initially pulled low during or after the power up sequence. the pin can then be allowed to float or be tied to v a / 2 to enter the des mode. this will ensure that the part enters the des mode correctly. 3) the automatic phase control should also be disabled if the input clock is interrupted or stopped for any reason.this is also the case if a large abrupt change in the clock frequency occurs. 4) if a calibration of the adc is required in auto des mode, the device must be returned to the normal mode of operation before performing a calibration cycle. once the calibration has been completed, the device can be returned to the auto des mode and operation can resume. 2.4.6 power down feature the power down pins (pd and pdq) allow the adc08d500 to be entirely powered down (pd) or the "q" channel to be powered down and the "i" channel to remain active. see section 1.1.7 for details on the power down feature. the digital data (+/-) output pins are put into a high imped- ance state when the pd pin for the respective channel is high. upon return to normal operation, the pipeline will con- tain meaningless information and must be flushed. if the pd input is brought high while a calibration is running, the device will not go into power down until the calibration sequence is complete. however, if power is applied and pd is already high, the device will not begin the calibration sequence until the pd input goes low. if a manual calibration is requested while the device is powered down, the calibra- tion will not begin at all. that is, the manual calibration input is completely ignored in the power down state. 2.5 the digital outputs the adc08d1000 demultiplexes the output data of each of the two adcs on the die onto two lvds output buses (total of four buses, two for each adc). for each of the two converters, the results of successive conversions started on the odd falling edges of the clk+ pin are available on one of the two lvds buses, while the results of conversions started on the even falling edges of the clk+ pin are available on the other lvds bus. this means that, the word rate at each lvds bus is 1/2 the adc08d1000 input clock rate and the two buses must be multiplexed to obtain the entire 1 gsps conversion result. since the minimum recommended input clock rate for this device is 200 msps (normal non des mode), the effective rate can be reduced to as low as 100 msps by using the results available on just one of the the two lvds buses and a 200 mhz input clock, decimating the 200 msps data by two. there is one lvds output clock pair (dclk+/-) available for use to latch the lvds outputs on all buses. whether the data is sent at the rising or falling edge of dclk is determined by the sense of the outedge pin, as described in section 2.4.3. ddr (double data rate) clocking can also be used. in this mode a word of data is presented with each edge of dclk, reducing the dclk frequency to 1/4 the input clock fre- quency. see the timing diagram section for details. the outv pin is used to set the lvds differential output levels. see section 2.4.4. the output format is offset binary. accordingly, a full-scale input level with v in + positive with respect to v in ? will pro- duce an output code of all ones, a full-scale input level with v in ? positive with respect to v in + will produce an output code of all zeros and when v in + and v in ? are equal, the output code will vary between codes 127 and 128. 2.6 power considerations a/d converters draw sufficient transient current to corrupt their own power supplies if not adequately bypassed. a 33 ? capacitor should be placed within an inch (2.5 cm) of the a/d converter power pins. a 0.1 ? capacitor should be placed as close as possible to each v a pin, preferably within one-half centimeter. leadless chip capacitors are preferred because they have low lead inductance. the v a and v dr supply pins should be isolated from each other to prevent any digital noise from being coupled into the analog portions of the adc. a ferrite choke, such as the jw miller fb20009-3b, is recommended between these supply lines when a common source is used for them. as is the case with all high speed converters, the adc08d500 should be assumed to have little power supply noise rejection. any power supply used for digital circuitry in a syatem where a lot of digital power is being consumed should not be used to supply power to the adc08d500. the adc supplies should be the same supply used for other analog circuitry, if not a dedicated supply. 2.6.1 supply voltage the adc08d500 is specified to operate with a supply volt- age of 1.9v 0.1v. it is very important to note that, while this device will function with slightly higher supply voltages, these higher supply voltages may reduce product lifetime. no pin should ever have a voltage on it that is in excess of the supply voltage or below ground by more than 150 mv, not even on a transient basis. this can be a problem upon application of power and power shut-down. be sure that the supplies to circuits driving any of the input pins, analog or digital, do not come up any faster than does the voltage at the adc08d500 power pins. the absolute maximum ratings should be strictly observed, even during power up and power down. a power supply that produces a voltage spike at turn-on and/or turn-off of power can destroy the adc08d500. the circuit of figure 15 will provide supply overshoot protection. many linear regulators will produce output spiking at power-on unless there is a minimum load provided. active devices draw very little current until their supply voltages reach a few hundred millivolts. the result can be a turn-on spike that can destroy the adc08d500, unless a minimum adc08d500 www.national.com 29
2.0 applications information (continued) load is provided for the supply. the 100 ? resistor at the regulator output provides a minimum output current during power-up to ensure there is no turn-on spiking. in the circuit of figure 15 , an lm317 linear regulator is satisfactory if its input supply voltage is 4v to 5v . if a 3.3v supply is used, an lm1086 linear regulator is recommended. the output drivers should have a supply voltage, v dr , that is within the range specified in the operating ratings table. this voltage should not exceed the v a supply voltage. if the power is applied to the device without a clock signal present, the current drawn by the device might be below 200 ma. this is because the adc08d500 gets reset through clocked logic and its initial state is random. if the reset logic comes up in the "on" state, it will cause most of the analog circuitry to be powered down, resulting in less than 100 ma of current draw. this current is greater than the power down current because not all of the adc is powered down. the device current will be normal after the clock is established. 2.6.2 thermal management the adc08d500 is capable of impressive speeds and per- formance at very low power levels for its speed. however, the power consumption is still high enough to require atten- tion to thermal management. for reliability reasons, the die temperature should be kept to a maximum of 130?c. that is, t a (ambient temperature) plus adc power consumption times ja (junction to ambient thermal resistance) should not exceed 130?c. this is not a problem if the ambient tempera- ture is kept to a maximum of +85?c as specified in the operating ratings section. please note that the following are general recommendations for mounting exposed pad devices onto a pcb. this should be considered the starting point in pcb and assembly pro- cess development. it is recommended that the process be developed based upon past experience in package mount- ing. the package of the adc08d500 has an exposed pad on its back that provides the primary heat removal path as well as excellent electrical grounding to the printed circuit board. the land pattern design for lead attachment to the pcb should be the same as for a conventional lqfp, but the exposed pad must be attached to the board to remove the maximum amount of heat from the package, as well as to ensure best product parametric performance. to maximize the removal of heat from the package, a ther- mal land pattern must be incorporated on the pc board within the footprint of the package. the exposed pad of the device must be soldered down to ensure adequate heat conduction out of the package. the land pattern for this exposed pad should be at least as large as th e5x5mmof the exposed pad of the package and be located such that the exposed pad of the device is entirely over that thermal land pattern. this thermal land pattern should be electrically con- nected to ground. a clearance of at least 0.5 mm should separate this land pattern from the mounting pads for the package pins. since a large aperture opening may result in poor release, the aperture opening should be subdivided into an array of smaller openings, similar to the land pattern of figure 16 . to minimize junction temperature, it is recommended that a simple heat sink be built into the pcb. this is done by including a copper area of about 2 square inches (6.5 square cm) on the opposite side of the pcb. this copper area may be plated or solder coated to prevent corrosion, but should not have a conformal coating, which could provide some thermal insulation. thermal vias should be used to connect these top and bottom copper areas. these thermal vias act as "heat pipes" to carry the thermal energy from the device side of the board to the opposite side of the board where it can be more effectively dissipated. the use of 9 to 16 thermal vias is recommended. the thermal vias should be placed on a 1.2 mm grid spacing and have a diameter of 0.30 to 0.33 mm. these vias should be barrel plated to avoid solder wicking into the vias during the soldering process as this wicking could cause voids in the solder between the package exposed pad and the ther- mal land on the pcb. such voids could increase the thermal resistance between the device and the thermal land on the board, which would cause the device to run hotter. if it is desired to monitor die temperature, a temperature sensor may be mounted on the heat sink area of the board near the thermal vias. .allow for a thermal gradient between the temperature sensor and the adc08d500 die of j-pad times typical power consumption = 2.8 x 1.6 = 4.5?c. allow- ing for a 5.5?c (including an extra 1?c) temperature drop from the die to the temperature sensor, then, would mean that maintaining a maximum pad temperature reading of 124.5?c will ensure that the die temperature does not ex- ceed 130?c, assuming that the exposed pad of the adc08d500 is properly soldered down and the thermal vias are adequate. (the inaccuracy of the temperature sensor is addtional to the above calculation). 20121454 figure 15. non-spiking power supply 20121421 figure 16. recommended package land pattern adc08d500 www.national.com 30
2.0 applications information (continued) 2.7 layout and grounding proper grounding and routing of all signals are essential to ensure accurate conversion. a single ground plane should be used instead of splitting the ground plane into analog and digital areas. since digital switching transients are composed largely of high frequency components, the skin effect tells us that total ground plane copper weight will have little effect upon the logic-generated noise. total surface area is more important than is total ground plane volume. coupling between the typically noisy digital circuitry and the sensitive analog cir- cuitry can lead to poor performance that may seem impos- sible to isolate and remedy. the solution is to keep the analog circuitry well separated from the digital circuitry. high power digital components should not be located on or near any linear component or power supply trace or plane that services analog or mixed signal components as the resulting common return current path could cause fluctuation in the analog input ?round return of the adc, causing excessive noise in the conversion result. generally, we assume that analog and digital lines should cross each other at 90? to avoid getting digital noise into the analog path. in high frequency systems, however, avoid crossing analog and digital lines altogether. clock lines should be isolated from all other lines, analog and digital. the generally accepted 90? crossing should be avoided as even a little coupling can cause problems at high frequen- cies. best performance at high frequencies is obtained with a straight signal path. the analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input. this is especially important with the low level drive required of the adc08d500. any external component (e.g., a filter capaci- tor) connected between the converters input and ground should be connected to a very clean point in the analog ground plane. all analog circuitry (input amplifiers, filters, etc.) should be separated from any digital components. 2.8 dynamic performance the adc08d500 is a.c. tested and its dynamic performance is guaranteed. to meet the published specifications and avoid jitter-induced noise, the clock source driving the clk input must exhibit low rms jitter. the allowable jitter is a function of the input frequency and the input signal level, as described in section 2.3. it is good practice to keep the adc clock line as short as possible, to keep it well away from any other signals and to treat it as a transmission line. other signals can introduce jitter into the clock signal. the clock signal can also introduce noise into the analog path if not isolated from that path. best dynamic performance is obtained when the exposed pad at the back of the package has a good connection to ground. this is because this path from the die to ground is a lower impedance than offered by the package pins. 2.9 using the serial interface the adc08d500 may be operated in the non-extended control (non-serial interface) mode or in the extended con- trol mode. table 6 and table 7 describe the functions of pins 3, 4, 14 and 127 in the non-extended control mode and the extended control mode, respectively. 2.9.1 non-extended control mode operation non-extended control mode operation means that the serial interface is not active and all controllable functions are con- trolled with various pin settings. that is, the full-scale range, single-ended or differential input and input coupling (a.c. or d.c.) are all controlled with pin settings. the non-extended control mode is used by setting pin 14 high or low, as opposed to letting it float. table 6 indicates the pin functions of the adc08d500 in the non-extended control mode. table 6. non-extended control mode operation (pin 14 high or low) pin low high floating 3 0.51 v p-p output 0.71 v p-p output n/a 4 outedge = neg outedge = pos ddr 127 caldly low caldly high des 14 650 mv p-p input range 870 mv p-p input range extended control mode pin 3 can be either high or low in the non-extended control mode. pin 14 must not be left floating to select this mode. see section 1.2 for more information. pin 4 can be high or low or can be left floating in the non-extended control mode. in the non-extended control mode, pin 4 high or low defines the edge at which the output data transitions. see section 2.4.3 for more information. if this pin is floating, the output clock (dclk) is a ddr (double data rate) clock (see section 1.1.5.3) and the output edge synchronization is irrelevant since data is clocked out on both dclk edges. pin 127, if it is high or low in the non-extended control mode, sets the calibration delay. if pin 127 is floating, the calibration delay is the same as it would be with this pin low and the converter performs dual edge sampling (des). table 7. extended control mode operation (pin 14 floating) pin function 3 sclk (serial clock) 4 sdata (serial data) 127 scs (serial interface chip select) 2.10 common application pitfalls driving the inputs (analog or digital) beyond the power supply rails. for device reliability, no input should not go more than 150 mv below the ground pins or 150 mv above the supply pins. exceeding these limits on even a transient basis may not only cause faulty or erratic operation, but may impair device reliability. it is not uncommon for high speed digital circuits to exhibit undershoot that goes more than a volt below ground. controlling the impedance of high speed lines and terminating these lines in their characteristic im- pedance should control overshoot. care should be taken not to overdrive the inputs of the adc08d500. such practice may lead to conversion inaccu- racies and even to device damage. incorrect analog input common mode voltage in the d.c. coupled mode. as discussed in section 1.1.4 and 2.2, the adc08d500 www.national.com 31
2.0 applications information (continued) input common mode voltage must remain within 50 mv of the v cmo output , which has a variability with temperature that must also be tracked. distortion performance will be degraded if the input common mode voltage is more than 50 mv from v cmo . using an inadequate amplifier to drive the analog input. use care when choosing a high frequency amplifier to drive the adc08d500 as many high speed amplifiers will have higher distortion than will the adc08d500, resulting in over- all system performance degradation. driving the v bg pin to change the reference voltage. as mentioned in section 2.1, the reference voltage is intended to be fixed to provide one of two different full-scale values (650 mv p-p and 870 mv p-p ). over driving this pin will not change the full scale value, but can otherwise upset opera- tion. driving the clock input with an excessively high level signal. the adc clock level should not exceed the level described in the operating ratings table or the input offset could change. inadequate clock levels. as described in section 2.3, insuf- ficient clock levels can result in poor performance. excessive clock levels could result in the introduction of an input offset. using a clock source with excessive jitter, using an excessively long clock signal trace, or having other signals coupled to the clock signal trace. this will cause the sampling interval to vary, causing excessive output noise and a reduction in snr performance. failure to provide adequate heat removal. as described in section 2.6.2, it is important to provide adequate heat re- moval to ensure device reliability. this can either be done with adequate air flow or the use of a simple heat sink built into the board. the backside pad should be grounded for best performance. adc08d500 www.national.com 32
physical dimensions inches (millimeters) unless otherwise noted notes: unless otherwise specified reference jedec registration ms-026, variation bfb. 128-lead exposed pad lqfp order number ADC08D500CIYB ns package number vnx128a national does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and national reserves the right at any time without notice to change said circuitry and specifications. for the most current product information visit us at www.national.com. life support policy national? products are not authorized for use as critical components in life support devices or systems without the express written approval of the president and general counsel of national semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. banned substance compliance national semiconductor manufactures products and uses packing materials that meet the provisions of the customer products stewardship specification (csp-9-111c2) and the banned substances and materials of interest specification (csp-9-111s2) and contain no banned substances as defined in csp-9-111s2. national semiconductor americas customer support center email: new.feedback@nsc.com tel: 1-800-272-9959 national semiconductor europe customer support center fax: +49 (0) 180-530 85 86 email: europe.support@nsc.com deutsch tel: +49 (0) 69 9508 6208 english tel: +44 (0) 870 24 0 2171 fran?ais tel: +33 (0) 1 41 91 8790 national semiconductor asia pacific customer support center email: ap.support@nsc.com national semiconductor japan customer support center fax: 81-3-5639-7507 email: jpn.feedback@nsc.com tel: 81-3-5639-7560 www.national.com high performance, low power, dual 8-bit, 500 msps a/d converter

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